Z8932320FEC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8932320FEC

16-BITDIGITAL SIGNALPROCESSORS

Zilog 

PRELIMINARY

Z89323/373/393

16-BIT DIGITAL SIGNAL PROCESSORS

Bank 13/EXT1 (Timer0) or Bank 14/EXT1 (Timer1)

Timer Control Register (TCTL)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Timer/Counter

0 Timer/Counter disabled (default)

1 Timer/Counter enabled

Input Select

00 Inputs have no effect

01 Reserved

10 UI0 Pin

11 UI1 Pin

Input Event

00 Low Level or Falling Edge

01 High Level or Rising Edge

10 Both Rising and Falling Edges

11 Reserved

Output Select

00 Outputs Unaffected

01 Reserved

10 Drive UO0 Pin

11 Drive UO1 Pin

Output Invert

0 Output asserted High on Timeout

1 Output asserted Low on Timeout

Timer Mode

Timer Output Modes

0000 Square Wave

Mode 0

0001 One-Shot

Mode 1

0010 PWM short (8-bit) Mode 2

0011 PWM long (16-bit) Mode 3

0100 Pulse Count Output Mode 4

0101 Triggered Count

Mode 5

0110 S/W Watch-Dog Mode Mode 6

0111 H/W Watch-Dog Mode Mode 7

Timer Input Modes

1000 Gated Count

Mode 8

1001 Period

Mode 9

1010 Pulse Count

Mode 10

1011 Gated Pulse Count Mode 11

Reserved

Test Mode*

0 Normal Operation

1 Factory Test Mode

*Note: The user should always

program this bit to be 0.

Figure 15. Register Bit Fields

DS95DSP0101 Q4/95

25

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