DSM2190F4
DECODE PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
s 8 Main Flash memory Sector Select (FS0-FS7)
signals with three product terms each
s 4 Secondary Flash memory Sector Select
(CSBOOT0-CSBOOT3) signals with three
product terms each
s 1 internal csiop select for DSM device control
and status registers (csiop is the base address
of the block of 256 byte locations)
s 1 JTAG Select signal (enables JTAG operations
on Port C when multiplexing JTAG signals with
general I/O signals)
s 3 external chip select output signals for Port D
pins, each with one product term.
Figure 14. DPLD Logic Array
I/O PORTS (PORT AB, ,C)
(INPUTS)
(16)
MCELLAB.FB [7:0] (Feedback)
(8)
MCELLBC.FB [7:0] (Feedback)
(8)
PG0-PG7
(8)
A[15:0]
(16)
PD[2:0]
(3)
CNTRL[2:0] (Read/Write Control Signals)(3)
RESET
(1)
RD_BSY
(1)
3
CSBOOT0
3
CSBOOT1 4 Secondary
Flash Memory
3
Sector Selects
CSBOOT2
3
CSBOOT3
3
FS0
3
FS1
3
FS2
3
8 Flash Main
FS3 Memory
3
Sector Selects
FS4
3
FS5
3
FS6
3
FS7
1
CSIOP
I/O Decoder
Select
1
JTAGSEL JTAG ISP
1
ECS0
1
ECS1
External Chip Selects
to PORT D
1
ECS2
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