DSM2190F4 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

DSM2190F4

DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)

STMicroelectronics 

DSM2190F4

COMPLEX PLD (CPLD)

The CPLD can be used to implement system logic

functions, such as loadable counters and shift reg-

isters, system mailboxes, handshaking protocols,

state machines, and random logic. See application

note AN1171 for details on how to specify logic us-

ing PSDsoft Express.

As shown in Figure 15, the CPLD has the following

blocks:

s 16 Input Macrocells (IMC)

s 16 Output Macrocells (OMC)

s Macrocell Allocator

s Product Term Allocator

s AND Array capable of generating up to 130

product terms

s Two I/O Ports.

Each of the blocks are described in the sections

that follow.

The Input Macrocells (IMC) and Output Macrocells

(OMC) are connected to the device internal data

bus and can be directly accessed by the DSP. This

enables the DSP software to load data into the

Output Macrocells (OMC) or read data from both

the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of sys-

tem logic and eliminates the need to connect the

data bus to the AND Array as required in most

standard PLD macro cell architectures.

Figure 15. Macrocell and I/O Port

Product Terms

from other

MacrocellS

DSP ADDRESS / DATA BUS

CPLD Macrocells

PRODUCT TERM

ALLOCATOR

PT PRESET

MCU DATA IN

MCU LOAD

DATA

LOAD

CONTROL

UP TO 10

PRODUCT TERMS

POLARITY

SELECT

PT

CLOCK

GLOBAL

CLOCK

CLOCK

SELECT

PT CLEAR

Macrocell

Out to

MCU

PR DI LD

D/T

Q

D/T/JK FF

SELECT

CK

CL

COMB.

/REG

SELECT

CPLD

OUTPUT

Macrocell

to

I/O Port

Alloc.

TO OTHER I/O PORTS

I/O PORTS

LATCHED

ADDRESS OUT

DATA

DQ

WR

MUX

CPLD OUTPUT

I/O Pin

PDR

INPUT

SELECT

DQ

DIR

WR

REG.

PT Output Enable (OE)

Macrocell Feedback

I/O Port Input

Input Macrocells

QD

PT INPUT LATCH GATE/CLOCK

Output Macrocell (OMC). Eight of the Output

Macrocells (OMC) are connected to Port B pins

and are named as McellAB0-McellAB7. The other

eight Macrocells are connected to Ports B or C

pins and are named as McellBC0-McellBC7.

OMCs may be used for internal feedback only

(buried registers), or their outputs may be routed

to external Port pins.

QD

G

AI04902B

The Output Macrocell (OMC) architecture is

shown in Figure 17. As shown in the figure, there

are native product terms available from the AND

Array, and borrowed product terms available (if

unused) from other Output Macrocells (OMC). The

polarity of the product term is controlled by the

XOR gate. The Output Macrocell (OMC) can im-

plement either sequential logic, using the flip-flop

26/61

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