DSM2190F4 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

DSM2190F4

DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)

STMicroelectronics 

DSM2190F4

DSP Bus Interface

The “no-glue logic” DSP Bus Interface allows di-

rect connection. DSP address, data, and control

signals connect directly to the DSM device. See

Figure 6 for typical connections.

DSP address, data and control signals are routed

to Flash memory, I/O control (csiop), OMCs, and

IMCs within the DMS. The DSP address range for

each of these components is specified in PSDsoft

ExpressTM.

I/O Ports

There are three programmable I/O ports: Ports B,

C, and D. Each of the ports is eight bits except Port

D, which is 3 bits. Each port pin is individually user

configurable, thus allowing multiple functions per

port. The ports are configured using PSDsoft Ex-

Figure 19. General I/O Port Architecture

pressTM or by the DSP writing to on-chip registers

in the csiop block.

The topics discussed in this section are:

s General Port architecture

s Port operating modes

s Port Configuration Registers (PCR)

s Port Data Registers

s Individual Port functionality.

General Port Architecture. The general archi-

tecture of the I/O Port block is shown in Figure 19.

Individual Port architectures are shown in Figure

20 to Figure 23. In general, once the purpose for a

port pin has been defined in PSDsoft ExpressTM,

that pin is no longer available for other purposes.

Exceptions are noted.

DATA OUT

REG.

DQ

WR

Macrocell Outputs

EXT CS

READ MUX

P

D

DATA IN

B

DATA OUT

OUTPUT

MUX

OUTPUT

SELECT

PORT PIN

ENABLE OUT

DIR REG.

DQ

WR

ENABLE PRODUCT TERM (.OE)

CPLD - INPUT

As shown in Figure 19, the ports contain an output

multiplexer whose select signals are driven by the

configuration bits determined by PSDsoft Express.

Inputs to the multiplexer include the following:

s Output data from the Data Out register (for MCU

I/O mode)

s CPLD Macrocell output (OMC)

Input

Macrocell

AI04905B

s External Chip Selects ESC0-2 from the DPLD to

Port D pins only.

The Port Data Buffer (PDB) is a tri-state buffer that

allows only one source at a time to be read by the

DSP. The Port Data Buffer (PDB) is connected to

the Internal Data Bus for feedback and can be

read by the DSP. The Data Out and Macrocell out-

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