STLC5048 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5048 Datasheet PDF : 45 Pages
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STLC5048
I/O Data Register channel #1 (DATA1)
Addr=04h; Reset Value=00h
Addr=05h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
0
0
D17
D16
D15
D14
D13
D12
D11
D10
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
0
1
D111
D110
D19
D18
When CS1 is active D111..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-
ister). For the I/O pins configured as inputs the corresponding D111..0 will be written by the values applied to
those pins while CS1 is low.
If bit 4 of CONF register (STA)=1 Static I/O mode:
In static mode CS pins are used as additional I/O pins. The CIO0..3 bits are used to define the direction of these pins.
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
0
0
CIO3
CIO2
CIO1
CIO0
CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3 is a static output, DATA is taken from DATA2 register bits 0..3.
I/O Data Register channel #2 (DATA2)
Addr=06h; Reset Value=00h
Addr=07h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
1
0
D27
D26
D25
D24
D23
D22
D21
D20
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
1
1
D211
D210
D29
D28
When CS2 is active D211..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-
ister). For the I/O pins configured as inputs the corresponding D211..0 will be written by the values applied to
those pins while CS2 is low.
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