STLC5048 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5048 Datasheet PDF : 45 Pages
| |||
STLC5048
Synchronous Check register (SYNCK)
Addr=23h; Reset Value=E4h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
0
1
1
1
1
1
0
0
1
0
0
This register contains a fixed code (E4h) that can be read to check the synchronisation of the MCU interface.
DSP Status Register (CTRLACK)
Addr=25h; Reset Value=01h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
INIT
CKEND
CKEND bit is 0 while the checksum calculation is performed: in the other time is always set to 1.
INIT bit becomes active (INIT = 1) after the DSP initialization. Normally it requires 70 us after the reset to be set to 1.
Checksum register (CKSUM)
Addr=26h; Reset Value=00h
Addr=27h; Reset Value=00h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
1
1
0
CK7
CK6
CK5
CK4
CK3
CK2
CK1
CK0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
1
1
1
CK15
CK14
CK13
CK12
CK11
CK10
CK9
CK8
The cheksum value is calculated every time the CKSTART instruction is performed and the result is available
after a proper delay (max 400 µs).
This register contains the cheksum value calculated on the contents of the following coefficient (each of 16 bits):
ZERO
KDF0_0 KDF0_1 KDF0_2 KDF1_0 KDF1_1 KDF1_2 KDF2_0 KDF2_1 KDF2_2 KDF3_0 KDF3_1 KDF3_2
AFE_CFF GRX0 GTX0 RFC0_0 ...... RFC0_16 XFC0_0 ...... XFC0_16 BFC0_0 ...... BFC0_25
ZFC0_0 ...... ZFC0_4 GRX1 GTX1 RFC1_0 ...... RFC1_16 XFC1_0 ...... XFC1_16 BFC1_0 ......BFC1_25
ZFC1_0 ...... ZFC1_4 GRX2 GTX2 RFC2_0 ......RFC2_16 XFC2_0 ...... XFC2_16 BFC2_0 ...... BFC2_25
ZFC2_0 ...... ZFC2_4 GRX3 GTX3 RFC3_0 ...... RFC3_16 XFC3_0 ...... XFC3_16 BFC3_0 ...... BFC3_25
ZFC3_0 ......ZFC3_4
20/45
Share Link: 