STLC5048 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5048 Datasheet PDF : 45 Pages
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STLC5048
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
1
0
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
1
0
1
1
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration of input A and B to
generate interrupt; spurious transitions shorter than the programmed value are ignored.
The time width can be calculated according to the formula:
Time - Width A = (TA7..0)*64µs
Time - Width B = (TB7..0)*64µs
If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will gen-
erate interrupt.
All the inputs, with or without persistency check, are sampled with a repetition rate of 32µs.
Interrupt Register (INT)
Addr=10h; Reset Value=00h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
0
0
0
0
ITV
IPCM
ICKF
ID3
ID2
ID1
ID0
In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related channel (SLIC). Any sin-
gle bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e. when channel n is disabled
to generate interrupt).
In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively:
ID0: is set High when the interrupt is requested from any the I/O11..0 lines.
ID2: is set High when the interrupt is requested from any the CS3..0 (configured as I/O).
ID0 and ID2 are cleared after reading related I/O register.
ID1 and ID3 are don’t care.
ITV = 1: If the interrupt has been generated by time-out violation on the MCU serial interface.
IPCM = 1: When transmit PCM data reading/writing test is enabled an interrupt is generated every time valid
data are available (RRD bit set to 1) or must be written (WRD bit set to 1). The interrupt is cleared after reading/
writing the data in the PCMRD/PCMWD register via the MCU interface.
ICKF = 1: If the interrupt has been generated by a clock failure on PCM port (MCLK).
The INT register is cleared after reading operation only if signals (alarm cause) are inactive.
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