PIC12F635/PIC16F636/639
12.9.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 “Timer0 Module” for operation of
the Timer0 module.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
LVDIF
LVDIE
TMR1IF
TMR1IE
C1IF
C1IE
C2IF(1)
C2IE(1)
EEIF
EEIE
OSFIF
OSFIE
CRIF
CRIE
T0IF
T0IE
INTF
INTE
RAIF
RAIE
PEIE
GIE
Note 1: PIC16F636/639 only.
12.9.3 PORTA INTERRUPT
An input change on PORTA change sets the RAIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
Interrupt to CPU
DS41232B-page 122
Preliminary
© 2005 Microchip Technology Inc.