PIC12F635/PIC16F636/639
FIGURE 12-8:
INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT(3)
(4)
INT pin
(1)
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
(1)
(5)
Interrupt Latency(2)
Instruction Flow
PC
Instruction
Fetched
PC
Inst (PC)
PC + 1
Inst (PC + 1)
PC + 1
—
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
Executed
Inst (PC – 1)
Inst (PC)
Dummy Cycle
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6: SUMMARY OF INTERRUPT REGISTERS
Address Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD,
WUR
Value on
all other
Resets
0Bh, 8Bh INTCON
0Ch
PIR1
8Ch
PIE1
GIE
EEIF
EEIE
PEIE
LVDIF
LVDIE
T0IE
CRIF
CRIE
INTE
C2IF(1)
C2IE(1)
RAIE
C1IF
C1IE
T0IF
OSFIF
OSFIE
INTF
—
—
RAIF 0000 0000 0000 0000
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
Legend:
Note 1:
x = unknown, u = unchanged, — = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
PIC16F636/639 only.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 123