PIC16F636T-I/SL(2005) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F636T-I/SL
(Rev.:2005)

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC12F635/PIC16F636/639

FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT

OSC1

CLKOUT(4)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

INT pin

INTF Flag

(INTCON<1>)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

TOST(2)

Interrupt Latency(3)

GIE bit

(INTCON<7>)

Processor in

Sleep

INSTRUCTION FLOW

PC

PC

Instruction

Fetched

Inst(PC) = Sleep

Instruction

Executed

Inst(PC – 1)

PC + 1

Inst(PC + 1)

Sleep

PC + 2

PC + 2

Inst(PC + 2)

Inst(PC + 1)

PC + 2

Dummy Cycle

0004h

Inst(0004h)

Dummy Cycle

0005h

Inst(0005h)

Inst(0004h)

Note 1:

2:

3:

4:

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

12.13 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP for verification purposes.

Note:

The entire data EEPROM and Flash

program memory will be erased when the

code protection is turned off. See the

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

12.14 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

DS41232B-page 128

Preliminary

© 2005 Microchip Technology Inc.

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