ST20-GP6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP6

GPS PROCESSOR

STMicroelectronics 

ST20-GP6

Set_Mask (address ‘interrupt base address + #C4’) allows bits to be set individually. Writing a ‘1’ in

this register sets the corresponding bit in the Mask register, a ‘0’ leaves the bit unchanged.

Clear_Mask (address ‘interrupt base address + #C8’) allows bits to be cleared individually. Writing

a ‘1’ in this register resets the corresponding bit in the Mask register, a ‘0’ leaves the bit

unchanged.

Pending register

The Pending register contains a bit per interrupt with each bit controlled by the corresponding

interrupt. A read can be used to examine the state of the interrupt controller while a write can be

used to explicitly trigger an interrupt.

A bit is set when the triggering condition for an interrupt is met. All bits are independent so that sev-

eral bits can be set in the same cycle. Once a bit is set, a further triggering condition will have no

effect. The triggering condition is independent of the Mask register.

The highest priority interrupt bit is reset once the interrupt controller has made an interrupt request

to the CPU.

The interrupt controller receives external interrupt requests and makes an interrupt request to the

CPU when it has a pending interrupt request of higher priority than the currently executing interrupt

handler.

Pending

Bit

Bit field

7:0

PendingInt7:0

Interrupt controller base address + #80

Function

Interrupt pending bit.

Table 5.4 Bit fields in the Pending register

Read/Write

The Pending register is mapped onto two additional addresses so that bits can be set or cleared

individually.

Set_Pending (address ‘interrupt base address + #84’) allows bits to be set individually. Writing a

‘1’ in this register sets the corresponding bit in the Pending register, a ‘0’ leaves the bit unchanged.

Clear_Pending (address ‘interrupt base address + #88’) allows bits to be cleared individually. Writ-

ing a ‘1’ in this register resets the corresponding bit in the Pending register, a ‘0’ leaves the bit

unchanged.

Note, if the CPU wants to write or clear some bits of the Pending register, the interrupts should be

masked (by writing or clearing the Mask register) before writing or clearing the Pending register.

The interrupts can then be unmasked.

Exec register

The Exec register keeps track of the currently executing and pre-empted interrupts. A bit is set

when the CPU starts running code for that interrupt. The highest priority interrupt bit is reset once

the interrupt handler executes a return from interrupt (iret).

Exec

Bit

7:0

Bit field

Interrupt7:0Exec

Interrupt controller base address + #100

Function

Set to 1 when the CPU starts running code for interrupt.

Table 5.5 Bit fields in the Exec register

Read/Write

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