ST20-GP6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP6

GPS PROCESSOR

STMicroelectronics 

ST20-GP6

IntPriority

Bit

Bit field

2:0

IntPriority

Interrupt level controller base address + #00 to #1C

Function

Determines the priority of each interrupt input.

IntPriority2:0 Asserts output interrupt

000

0 (lowest priority)

001

1

010

2

011

3

100

4

101

5

110

6

111

7 (highest priority)

Read/Write

Table 6.2 IntPriority register format - 1 register per interrupt

InputInterrupts register

The InputInterrupts register is a read only register. It contains a vector which shows all of the input

interrupts, so bit 0 of the read data corresponds to InterruptIn0, bit 1 corresponds to InterruptIn1.

Inputinterrupts

Bit

Bit field

1:0

InterruptIn-0

Interrupt level controller base address + #48

Function

Input interrupt levels.

Read only

Table 6.3 InputInterrupts register format

Low power controller support registers

The interrupt level controller has 2 additional registers to support the low power controller (see

Chapter 11 on page 66). The external interrupts can be used to provide a wake-up from power-

down mode.

The IntLPEnable register can be programmed for each interrupt to cause the interrupt to wake-up

the ST20-GP6 from power-down mode. The wake-up occurs when the interrupt goes either high or

low, depending on the setting of the respective bit in the IntActiveHigh register.

IntLPEnable

The IntLPEnable register can be set to enable a wake-up from power-down mode when the inter-

rupt occurs.

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