ST20-GP6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP6

GPS PROCESSOR

STMicroelectronics 

ST20-GP6

7 Instruction set

This chapter provides information on the ST20-C2 instruction set. It contains tables listing all the

instructions, and where applicable provides details of the number of processor cycles taken by an

instruction.

The instruction set has been designed for simple and efficient compilation of high-level languages.

All instructions have the same format, designed to give a compact representation of the operations

occurring most frequently in programs.

Each instruction consists of a single byte divided into two 4-bit parts. The four most significant bits

(MSB) of the byte are a function code and the four least significant bits (LSB) are a data value, as

shown in Figure 7.1.

Function

Data

7

43

0

Figure 7.1 Instruction format

For further information on the instruction set refer to the ST20C2/C4 Instruction Set Manual (docu-

ment number 72-TRN-273).

7.1 Instruction cycles

Timing information is available for some instructions. However, it should be noted that many

instructions have ranges of timings which are data dependent.

Where included, timing information is based on the number of clock cycles assuming any memory

accesses are to 2 cycle internal memory and no other subsystem is using memory. Actual time will

be dependent on the speed of external memory and memory bus availability.

Note that the actual time can be increased by:

1 the instruction requiring a value on the register stack from the final memory read in the pre-

vious instruction – the current instruction will stall until the value becomes available.

2 the first memory operation in the current instruction can be delayed while a preceding

memory operation completes - any two memory operations can be in progress at any time,

any further operation will stall until the first completes.

3 memory operations in current instructions can be delayed by access by instruction fetch or

subsystems to the memory interface.

4 there can be a delay between instructions while the instruction fetch unit fetches and par-

tially decodes the next instruction – this will be the case whenever an instruction causes the

instruction flow to jump.

Note that the instruction timings given refer to ‘standard’ behavior and may be different if, for exam-

ple, traps are set by the instruction.

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