TS68230 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TS68230

HMOS PARALLEL INTERFACE/TIMER

STMicroelectronics 

TS68230

Programmable Options Mode 3 - Port A Submode XX and Port B Submode XX

PACR

76

XX

PACR

543

XX0

XX1

PACR

2

0

1

PACR

1

0

1

PACR

0

0

1

PBCR

76

XX

PBCR

543

XX0

XX1

PBCR

2

0

1

PBCR

1

0

1

PBCR

0

X

Port A Submode

Submode XX.

H2 Control

Output pin - interlocked output handshake protocol, H2S status always cleared.

Output pin - pulsed output handshake protocol, H2S status always cleared.

H2 Interrupt Enable

The H2 interrupt is disabled.

The H2 interrupt is enabled.

H1 SVCRQ Enable

The H1 interrupt and DMA request are disabled.

The H1 interrupt and DMA request are enabled.

H1 Status Control

The H1 status bit is set when either the port B initial or final output latch can accept new data.

It is clear when both latches are full and cannot accept new data.

The H1S status bit is set when both of the port B output latches are empty. It is clear when at

least one latch is full.

Port B Submode

Submode XX.

H4 Control

Output pin - interlocked input handshake protocol, H4S is always clear.

Output pin - pulsed input handshake, H4S is always clear.

H4 Interrupt Enable

The H4 interrupt is disabled.

The H4 interrupt is enabled.

H3 SVCRQ Enable

The H3 interrupt and DMA request are disabled.

The H3 interrupt and DMA request are enabled.

H3 Status Control

The H3S status bit is set anytime input data is present in the double-buffered input path.

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