TS68230 View Datasheet(PDF) - STMicroelectronics
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TS68230 Datasheet PDF : 61 Pages
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TS68230
SECTION 4
PROGRAMMER’S MODEL
This section describes the internal accessible regis-
ter organization as represented in table 1.3 located
at the end of this document and in table 4.1. Address
space within the address map is reserved for future
expansion.
Table 4.1 : PI/T Register Addressing Assignments.
Register
Register
Select Bits
54321
Accessible
Affected by
Reset
Affected by
Read Cycle
Port General Control Register
(PGCR) 0 0 0 0 0
RW
Yes
No
Port Service Request Register
(PSRR) 0 0 0 0 1
RW
Yes
No
Port A Data Direction Register
(PADDR) 0 0 0 1 0
RW
Yes
No
Port B Data Direction Register
(PBDDR) 0 0 0 1 1
RW
Yes
No
Port C Data Direction Register
(PCDDR) 0 0 1 0 0
RW
Yes
No
Port Interrupt Vector Register
(PIVR) 0 0 1 0 1
RW
Yes
No
Port A Control Register
(PACR) 0 0 1 1 0
RW
Yes
No
Port B Control Register
(PBCR) 0 0 1 1 1
RW
Yes
No
Port A Data Register
(PADR) 0 1 0 0 0
RW
No
**
Port B Data Register
(PBDR) 0 1 0 0 1
RW
No
**
Port A Alternate Register
(PAAR) 0 1 0 1 0
R
No
No
Port B Alternate Register
(PBAR) 0 1 0 1 1
R
No
No
Port C Data Register
(PCDR) 0 1 1 0 0
RW
No
No
Port Status Register
(PSR) 0 1 1 0 1
R W*
Yes
No
Timer Control Register
(TCR) 1 0 0 0 0
RW
Yes
No
Timer Interrupt Vector Register
(TIVR) 1 0 0 0 1
RW
Yes
No
Counter Preload Register High
(CPRH) 1 0 0 1 1
RW
No
No
Counter Preload Register Middle
(CPRM) 1 0 1 0 0
RW
No
No
Counter Preload Register Low
(CPRL) 1 0 1 0 1
RW
No
No
Count Register High
(CNTRH) 1 0 1 1 1
R
No
No
Count Register Middle
(CNTRM) 1 1 0 0 0
R
No
No
Count Register Low
(CNTRL) 1 1 0 0 1
R
No
No
Timer Status Register
(TSR) 1 1 0 1 0
R W*
Yes
No
* A write to this register may perform a special resetting opera-
R = Read.
W = Write.
Throughout this section the following conventions
are maintained :
1. A read from a reserved location in the map re-
sults in a read from the "null register". The null
register returns all zeros for data and results in
a normal bus cycle. A write to one of these lo-
cations results in a normal bus cycle, but writ-
ten data is ignored.
2. Unused bits of a defined register are denoted
by "*" and are read as zeros ; written data is i-
gnored.
3. Bits that are unused in the chosen mode/sub-
mode but are used in others are denoted by
"X", and are readable and writable. Their
content, however, is ignored in the chosen
mode/submode.
4. All registers are addressable as 8-bit quanti-
ties. To facilitate operation with the MOVEP
instruction and the DMAC, addresses are or-
dered such that certain sets of registers may
also be accessed as words (two bytes) or long
words (four bytes).
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