SI3019-F-FM View Datasheet(PDF) - Silicon Laboratories
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Description
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SI3019-F-FM Datasheet PDF : 128 Pages
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Si3050 + Si3011/18/19
CVT[7:0] bits. Therefore, only positive numbers should
be used as a threshold.
5.16. DC Termination
The DAA has programmable settings for the dc
impedance, current limiting, minimum operational loop
current and TIP/RING voltage. The dc impedance of the
DAA is normally represented with a 50 slope as
shown in Figure 23, but can be changed to an 800
slope by setting the DCR bit. This higher dc termination
presents a higher resistance to the line as loop current
increases.
The MINI[1:0] bits select the minimum operational loop
current for the DAA, and the DCV[1:0] bits adjust the
DCT pin voltage, which affects the TIP/RING voltage of
the DAA. These bits allow important trade-offs to be
made between signal headroom and minimum
operational loop current. Increasing TIP/RING voltage
increases signal headroom, whereas decreasing the
TIP/RING voltage allows compliance to PTT standards
in low-voltage countries, such as Japan. Increasing the
minimum operational loop current above 10 mA also
increases signal headroom and prevents degradation of
the signal level in low-voltage countries.
FCC DCT Mode
12
11
10
9
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
Figure 23. FCC Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0
For applications requiring current limiting per the TBR21
standard, the ILIM bit may be set to select this mode. In
this mode, the dc I/V curve is changed to a 2000
slope above 40 mA, as shown in Figure 24. This allows
the DAA to operate with a 50 V, 230 feed, which is the
maximum linefeed specified in the TBR21 standard.
TBR21 DCT Mode
45
40
35
30
Finally, Australia has separate dc termination
requirements for line seizure versus line hold. Japan
mode (only available with the Si3018 or Si3019) may be
used to satisfy both requirements. However, if a higher
transmit level for modem operation is desired, switch to
FCC mode 500 ms after the initial off-hook. This
satisfies the Australian dc termination requirements.
5.17. AC Termination
The Si3050 + Si3011 chipset provides two ac
termination impedances. The Si3050 + Si3018 chipset
provides four ac termination impedances. The
ACIM[3:0] bits in Register 30 are used to select the ac
impedance setting. The two available settings for the
Si3050 + Si3011 chipset are listed in Table 16. The four
available settings for the Si3018 are listed in Table 17. If
an ACIM[3:0] setting other than the four listed in
Table 16 or Table 17 is selected, the ac termination is
forced to 600 (ACIM[3:0] = 0000). The programmable
digital hybrid can be used to further reduce near-end
echo for each of the four listed ac termination settings.
See "5.28. Transhybrid Balance" on page 38 for details.
Table 16. AC Termination Settings for the
Si3011 Line-Side Device
ACIM[3:0]
AC Termination
0000 600
0001 210 + (750 || 150 nF) and 275 +
(780 || 150 nF)
25
20
15
10
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
Figure 24. TBR21 Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 1
Rev. 1.5
31
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