SI3019-F-FM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3019-F-FM

PROGRAMMABLE VOICE DAA SOLUTIONS

Silicon Laboratories 

Si3050 + Si3011/18/19

Table 20. PCM or GCI Highway Mode Selection

SCLK

SDI

Mode Selected

1

X

0

0

0

1

PCM Mode

GCI Mode,

B2 Channel used

GCI Mode,

B1 Channel used

Note: Values shown are the states of the pins at the rising edge of

RESET.

Table 21. Pin Functionality in PCM or GCI Highway Mode

Pin Name

PCM Mode

GCI Mode

SDI_THRU

SPI Data Throughput pin for Daisy Chaining

Operation (Connects to the SDI pin of the

subsequent device in the daisy chain)

Sub-frame

Selector, bit 2

SCLK

SPI Clock Input

PCM/GCI Mode Selector

SDI

SPI Serial Data Input

B1/B2 Channel Selector

SDO

SPI Serial Data Output

Sub-frame

Selector, bit 1

CS

SPI Chip Select

Sub-frame

Selector, bit 0

FSYNC

PCM Frame Sync Input

GCI Frame Sync Input

PCLK

PCM Input Clock

GCI Input Clock

DTX

PCM Data Transmit

GCI Data Transmit

DRX

PCM Data Receive

GCI Data Receive

Note: This table denotes pin functionality after the rising edge of RESET and mode selection.

5.32. PCM Highway

The Si3050 contains a flexible programmable interface for the transmission and reception of digital PCM samples.

PCM data transfer is controlled via the PCLK and FSYNC inputs, the PCM Transmit and Receive Start Count

registers (Registers 34–37), and the PCM Mode Select register (Register 33). The interface can be configured to

support from 4 to 128 8-bit timeslots in each frame, which corresponds to PCLK frequencies of 256 kHz to

8.192 MHz in power of 2 increments. Time slot assignment and data delay from FSYNC edge are handled via the

TXS and RXS registers. These 10-bit values are programmed with the number of PCLK cycles following the rising

edge of FSYNC until the data transfer begins. Because the Si3050 looks for the rising edge of FSYNC, both long

and short FSYNC pulse widths can be accommodated. A value of 0 in the PCM Transmit and Receive Start Count

registers signifies that the MSB of the data should occur in the same cycle as the rising edge of FSYNC.

40

Rev. 1.5

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