ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

Device architecture

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Table 8. System registers (group E) (continued)

Register

Description

R227 (E3h)

R226 (E2h)

R225 (E1h)

R224 (E0h)

PORT3 DATA REG.

PORT2 DATA REG.

PORT1 DATA REG.

PORT0 DATA REG.

6.3.1

Note:

Central interrupt control register

Please refer to Section 9: Interrupts for a detailed description of the ST9 interrupt

philosophy.

CENTRAL INTERRUPT CONTROL REGISTER (CICR)

R230 - Read/Write

Register Group: E (System)

Reset Value: 1000 0111 (87h)

7

0

GCEN

TLIP

TLI

IEN

IAM

CPL2

CPL1

CPL0

Bit 7 = GCEN: Global Counter Enable.

This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed

with the CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer)

in order to enable the Timers when both bits are set. This bit is set after the Reset cycle.

If an MFT is not included in the ST9 device, then this bit has no effect.

Bit 6 = TLIP: Top Level Interrupt Pending.

This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can

also be set by software to simulate a Top Level Interrupt Request.

0: No Top Level Interrupt pending

1: Top Level Interrupt pending

Bit 5 = TLI: Top Level Interrupt bit.

0: Top Level Interrupt is acknowledged depending on the TLNM bit in the NICR Register.

1: Top Level Interrupt is acknowledged depending on the IEN and TLNM bits in the NICR

Register (described in the Interrupt chapter).

Bit 4 = IEN: Interrupt Enable.

This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is

modified implicitly by iret, ei and di instructions or by an interrupt acknowledge cycle. It

can also be explicitly written by the user, but only when no interrupt is pending. Therefore,

the user should execute a di instruction (or guarantee by other means that no interrupt

request can arrive) before any write operation to the CICR register.

0: Disable all interrupts except Top Level Interrupt.

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Doc ID 8848 Rev 7

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