ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

Device architecture

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Figure 23. Pointing to two groups of 8 registers

BLOCK

NUMBER

31

30

29

28

27

26

25

addressed by

BLOCK 7

9

8

7

6

5

4

3

2

1

0

REGISTER

GROUP

REGISTER

FILE

F

REGISTER

POINTER 0

&

REGISTER

POINTER 1

E

set by:

srp0 #2

&

srp1 #7

D

instructions

point to:

4

r15

3

r8

GROUP 3

2

1

r7

r0

0

GROUP 1

addressed by

BLOCK 2

6.3.4

Paged registers

Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged

registers hold data and control information relating to the on-chip peripherals, each

peripheral always being associated with the same pages and registers to ensure code

compatibility between ST9 devices. The number of these registers depends on the

peripherals present in the specific ST9 device. In other words, pages only exist if the

relevant peripheral is present.

The paged registers are addressed using the normal register addressing modes, in

conjunction with the Page Pointer register, R234, which is one of the System registers. This

register selects the page to be mapped to Group F and, once set, does not need to be

changed if two or more registers on the same page are to be addressed in succession.

Thus the instructions:

spp #5

ld R242, r4

60/523

Doc ID 8848 Rev 7

Share Link: