ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Device architecture

will load the contents of working register r4 into the third register of page 5 (R242).

Warning:

During an interrupt, the PPR register is not saved

automatically in the stack. If needed, it should be

saved/restored by the user within the interrupt routine.

PAGE POINTER REGISTER (PPR)

R234 - Read/Write

Register Group: E (System)

Reset value: xxxx xx00 (xxh)

7

0

PP5

PP4

PP3

PP2

PP1

PP0

0

0

Bits 7:2 = PP[5:0]: Page Pointer.

These bits contain the number (in the range 0 to 63) of the page specified in the spp

instruction. Once the page pointer has been set, there is no need to refresh it unless a

different page is required.

6.3.5

Bits 1:0: Reserved. Forced by hardware to 0.

Mode register

The Mode Register allows control of the following operating parameters:

● Selection of internal or external System and User Stack areas,

● Management of the clock frequency,

● Enabling of Bus request and Wait signals when interfacing to external memory.

MODE REGISTER (MODER)

R235 - Read/Write

Register Group: E (System)

Reset value: 1110 0000 (E0h)

7

0

SSP

USP

DIV2

PRS2

PRS1

PRS0

BRQEN

HIMP

Bit 7 = SSP: System Stack Pointer.

This bit selects an internal or external System Stack area.

0: External system stack area, in memory space.

1: Internal system stack area, in the Register File (reset state).

Bit 6 = USP: User Stack Pointer.

This bit selects an internal or external User Stack area.

0: External user stack area, in memory space.

1: Internal user stack area, in the Register File (reset state).

Doc ID 8848 Rev 7

61/523

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