ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

Device architecture

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit

address (see Figure 28).

6.7

6.7.1

MMU registers

The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of

the EMR2 register.

Most of these registers do not have a default value after reset.

DPR[3:0]: data page registers

The DPR[3:0] registers allow access to the entire 4-Mbyte memory space composed of 256

pages of 16 Kbytes.

Data page register relocation

If these registers are to be used frequently, they may be relocated in register group E, by

programming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0]

registers are located at R224-227 in place of the Port 0-3 Data Registers, which are re-

mapped to the default DPR's locations: R240-243 page 21.

Data Page Register relocation is illustrated in Figure 26.

Figure 28. Addressing via CSR, ISR, and DMASR

CSR

MMU registers

DMASR

ISR

16-bit virtual address

1

2

3

1 Fetching program

instruction

2 Data Memory

accessed in DMA

3 Fetching interrupt

instruction or DMA

access to Program

Memory

6 bits

22-bit physical address

DATA PAGE REGISTER 0 (DPR0)

R240 - Read/Write

Register Page: 21

Reset value: undefined

This register is relocated to R224 if EMR2.5 is set.

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Doc ID 8848 Rev 7

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