ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

Device architecture

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

6.5

Memory management unit

The CPU Core includes a Memory Management Unit (MMU) which must be programmed to

perform memory accesses (even if external memory is not used).

The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2,

which may be written and read by the user program. These registers are mapped within

group F, Page 21 of the Register File. The 7 registers may be sub-divided into 2 main

groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit

registers (CSR, ISR, and DMASR). The first group is used to extend the address during

Data Memory access (DPR[3:0]). The second is used to manage Program and Data

Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR),

and DMA transfers (DMASR or ISR).

Figure 26. Page 21 registers

Page 21

FFh

FEh

FDh

FCh

FBh

FAh

F9h

DMASR

F8h

ISR

F7h

F6h

EMR2

F5h

EMR1

F4h

CSR

F3h

DPR3

F2h

DPR2

F1h

DPR1

F0h

DPR0

R255

R254

R253

R252

R251

R250

R249

R248

R247

R246

R245

R244

R243

R242

R241

R240

MMU

EM

MMU

MMU

Relocation of P[3:0] and DPR[3:0] Registers

SSPLR

SSPHR

USPLR

USPHR

MODER

PPR

RP1

RP0

FLAGR

CICR

P5DR

P4DR

P3DR

P2DR

P1DR

P0DR

DMASR

ISR

EMR2

EMR1

CSR

DPR3

DPR2

DPR1

DPR0

Bit DPRREM=0

(default setting)

SSPLR

SSPHR

USPLR

USPHR

MODER

PPR

RP1

RP0

FLAGR

CICR

P5DR

P4DR

DPR3

DPR2

DPR1

DPR0

DMASR

ISR

EMR2

EMR1

CSR

P3DR

P2DR

P1DR

P0DR

Bit DPRREM=1

6.6

6.6.1

Address space extension

To manage 4 Mbytes of addressing space, it is necessary to have 22 address bits. The

MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a

22-bit physical address. There are 2 different ways to do this depending on the memory

involved and on the operation being performed.

Addressing 16-Kbyte pages

This extension mode is implicitly used to address Data memory space if no DMA is being

performed.

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Doc ID 8848 Rev 7

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