P30-65nm SBC
Table 34: System Interface Information
Offset Length
Description
Add
Hex
Code
Value
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
VCC logic supply minimum program/erase voltage
1
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1B: --17
1.7V
VCC logic supply maximum program/erase voltage
1
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1C: --20
2.0V
VPP [programming] supply minimum program/erase voltage
1
bits 0-3 BCD 100 mV
1D: --85
8.5V
bits 4-7 HEX volts
VPP [programming] supply maximum program/erase voltage
1
bits 0-3 BCD 100 mV
1E: --95
9.5V
bits 4-7 HEX volts
1
“n” such that typical single word program time-out = 2n µ-sec 1F: --06
64µs
1
“n” such that typical full buffer write time-out = 2n µ-sec
20: --09 512µs
1
“n” such that typical block erase time-out = 2n m-sec
21: --09
0.5s
1
“n” such that typical full chip erase time-out = 2n m-sec
22: --00
NA
1
“n” such that maximum word program time-out = 2n times
typical
23: --02 256µs
1
“n” such that maximum buffer write time-out = 2n times
typical
24: --02 2048µs
1
“n” such that maximum block erase time-out = 2n times
typical
25: --03
4s
1
“n” such that maximum chip erase time-out = 2n times typical 26: --00
NA
Datasheet
64
Apr 2010
Order Number: 208033-02