JS28F128P30BF65 View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

Manufacturer

JS28F128P30BF65

Axcell™ P30-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC)

Numonyx -> Micron 

P30-65nm SBC

Table 25: AC Read Specifications (Sheet 2 of 2)

Num

Symbol

Parameter

Min

Max

Unit Notes

Synchronous Specifications(5)

R301

R302

R303

R304

tAVCH/L

tVLCH/L

tELCH/L

Address setup to CLK

ADV# low setup to CLK

CE# low setup to CLK

tCHQV / tCLQV CLK to output valid

9

9

9

Easy BGA/QUAD+

-

TSOP

-

-

ns

-

ns

-

ns

1,6

17

ns

20

ns

R305

tCHQX

Output hold from CLK

Easy BGA/QUAD+

3

TSOP

5

-

ns

1,6

-

ns

1,6

R306

R307

tCHAX

tCHTV

Address hold from CLK

CLK to WAIT valid

10

-

ns

1,4,6

Easy BGA/QUAD+

-

17

ns

1,6

TSOP

-

20

ns

1,6

R311

R312

tCHVL

tCHTX

CLK Valid to ADV# Setup

WAIT Hold from CLK

3

Easy BGA/QUAD+

3

TSOP

5

-

ns

1

-

ns

1,6

-

ns

1,6

Notes:

1.

See Figure 16, “AC Input/Output Reference Waveform” on page 48 for timing measurements and

max allowable input slew rate.

2.

OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

3.

Sampled, not 100% tested.

4.

Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

5.

Synchronous burst read mode is not supported with TTL level inputs.

6.

Applies only to subsequent synchronous reads.

Figure 19: Asynchronous Single-Word Read (ADV# Low)

Address [A]

ADV#[V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

RST# [P]

R1

R2

R3

R4

R15

R7

R6

R5

R8

R9

R17

Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).

Datasheet

51

Apr 2010

Order Number:208033-02

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