P30-65nm SBC
Figure 24: Synchronous Burst-Mode Four-Word Read Timing
y
CLK [C]
R302
R301 R306
R2
R101
Address [A]
A
ADV# [V]
R105
R106
R102
R303
R3
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
R15
R307
R4
R7
R304
R304
R305
Q0
Q1
Q2
R8
R9
R17
R10
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
15.4
AC Write Specifications
Table 26: AC Write Specifications (Sheet 1 of 2)
Num Symbol
Parameter
W1
tPHWL
RST# high recovery to WE# low
W2
tELWL
CE# setup to WE# low
W3
tWLWH
WE# write pulse width low
W4
tDVWH
Data setup to WE# high
W5
tAVWH
Address setup to WE# high
W6
tWHEH
CE# hold from WE# high
W7
tWHDX
Data hold from WE# high
W8
tWHAX
Address hold from WE# high
W9
tWHWL
WE# pulse width high
W10
tVPWH
VPP setup to WE# high
W11
tQVVL
VPP hold from Status read
W12
tQVBL
WP# hold from Status read
W13
tBHWH
WP# setup to WE# high
W14
tWHGL
WE# high to OE# low
W16
tWHQV
WE# high to read valid
Write to Asynchronous Read Specifications
W18
tWHAV
WE# high to Address valid
Min
150
0
50
50
50
0
0
0
20
200
0
0
200
0
tAVQV + 35
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,3
1,2,4
1,2,12
1,2
1,2,5
1,2,3,7
1,2,3,7
1,2,9
1,2,3,6,10
0
-
ns
1,2,3,6,8
Datasheet
54
Apr 2010
Order Number: 208033-02