ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLITE39F2U6TR

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI™

STMicroelectronics 

ST7LITE3xF2

OPERATING CONDITIONS (Cont’d)

13.3.1.2 Devices with tested for TA = -40 to +125°C @ VDD = 3.0 to 3.6V

Symbol

Parameter

Conditions

fRC1)

ACCRC

IDD(RC)

tsu(RC)

fPLL

tLOCK

tSTAB

ACCPLL

tw(JIT)

JITPLL

IDD(PLL)

Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD= 3.3V

quency

RCCR=RCCR12) ,TA=25°C,VDD= 3.3V

Accuracy of Internal RC TA=25°C, VDD=3.0 to 3.6V

oscillator when calibrated TA=-40 to +85°C, VDD=3.0 to 3.6V

with RCCR=RCCR1 2)3) TA=-40 to +125°C, VDD=3.0 to 3.6V

RC oscillator current con-

sumption

TA=25°C,VDD=3.3V

RC oscillator setup time

x4 PLL input clock

PLL Lock time7)

PLL Stabilization time7)

TA=25°C,VDD=3.3V

x4 PLL Accuracy

fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V

fRC = 1MHz@TA=-40 to +125°C, VDD= 3.3V

PLL jitter period

fRC = 1MHz

PLL jitter (∆fCPU/fCPU)

PLL current consumption TA=25°C

Min Typ Max

630

995 1000 1005

-1

+1

-3

+3

-3

+3

5003)4)

1

2

4

0.16)

0.16)

85)

15)

4503)

102)

Unit

kHz

%

µA

µs

MHz

ms

ms

%

%

kHz

%

µA

Notes:

1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23.

3. Data based on characterization results, not tested in production

4. Measurement made with RC calibrated at 1MHz.

5. Guaranteed by design.

6. Averaged over a 4ms period. After the LOCKED bit is s et, a period of tSTAB is required to reach ACCPLL accuracy

7. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24.

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