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ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics

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Description
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ST7PLITE39F2U6TR Datasheet PDF : 173 Pages
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ST7LITE3xF2
driven by external square wave, LVD disabled.
3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
Figure 77. Typical IDD in RUN vs. fCPU
8MHz
7.0
6.0
4MHz
5.0
1MHz
4.0
3.0
2.0
1.0
0.0
2.4
2.7
3.3
4
5
6
Vdd (V)
Figure 78. Typical IDD in SLOW vs. fCPU
1000.00
8MHz
800.00
4MHz
600.00
1MHz
400.00
200.00
0.00
2.4
2.7
3.3
4
5
6
Vdd (V)
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