ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLITE39F2U6TR

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI™

STMicroelectronics 

ST7LITE3xF2

EMC CHARACTERISTICS (Cont’d)

13.7.2 EMI (Electromagnetic Interference)

Based on a simple application running on the

product (toggling two LEDs through the I/O ports),

the product is monitored in terms of emission. This

emission test is in line with the norm SAE J 1752/

3 which specifies the board and the loading of

each pin.

Symbol

Parameter

Conditions

Monitored

Frequency Band

SEMI Peak level

VDD=5V, TA=+25°C,

SO20 package,

0.1MHz to 30MHz

30MHz to 130MHz

conforming to SAE J 1752/3 130MHz to 1GHz

SAE EMI Level

Note:

1. Data based on characterization results, not tested in production.

Max vs. [fOSC/fCPU]

8/4MHz 16/8MHz

16

17

20

25

15

16

3

3.5

Unit

dBµV

-

13.7.3 Absolute Maximum Ratings (Electrical

Sensitivity)

Based on two different tests (ESD and LU) using

specific measurement methods, the product is

stressed in order to determine its performance in

terms of electrical sensitivity.

13.7.3.1 Electrostatic Discharge (ESD)

Electrostatic discharges (a positive then a nega-

tive pulse separated by 1 second) are applied to

the pins of each sample according to each pin

combination. The sample size depends on the

number of supply pins in the device (3 parts*(n+1)

supply pin). Two models can be simulated: Human

Body Model and Machine Model. This test con-

forms to the JESD22-A114A/A115A standard. For

more details, refer to the application note AN1181.

ESD Absolute Maximum Ratings

Symbol

VESD(HBM)

Ratings

Electro-static discharge voltage

(Human Body Model)

Conditions

TA=+25°C

Maximum value 1) Unit

6000

V

Notes:

1. Data based on characterization results, not tested in production.

13.7.3.2 Static latch-up

Two complementary static tests are required on 10

parts to assess the latch-up performance.

A supply overvoltage (applied to each power sup-

ply pin) and a current injection (applied to each in-

put, output and configurable I/O pin) are per-

formed on each sample. These tests are compliant

with the EIA/JESD 78 IC latch-up standard.

Electrical Sensitivities

Symbol

Parameter

Conditions

Class 1)

LU

Static latch-up class

TA=+25°C

A

Note:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

147/173

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