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ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics

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Description
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ST7PLITE39F2U6TR Datasheet PDF : 173 Pages
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ST7LITE3xF2
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
TA = -40°C to 125°C, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Unit
VIL Input low level voltage
VIH Input high level voltage
Vhys Schmitt trigger voltage hysteresis 1)
VOL Output low level voltage 2)
RON Pull-up equivalent resistor 3) 1)
tw(RSTL)out Generated reset pulse duration
th(RSTL)in External reset pulse hold time 4)
tg(RSTL)in Filtered glitch duration
VSS - 0.3
0.7xVDD
0.3xVDD V
VDD + 0.3
1
V
VDD=5V
IIO=+5mA TA125°C
TA125°C
IIO=+2mA TA125°C
TA125°C
0.5 1.0
-
1.2
V
0.45 0.7
-
0.9
VDD=5V TA125°C
10
46
70 k
VDD=3V
91
k
Internal reset sources
30
µs
20
µs
200
ns
Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 132 and
the sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
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