LFSC3GA40E-7FF1020I View Datasheet(PDF) - Lattice Semiconductor

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Description

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LFSC3GA40E-7FF1020I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeSC/M Family Data Sheet

PURESPEED I/O Buffer Banks

LatticeSC devices have seven PURESPEED I/O buffer banks; each is capable of supporting multiple I/O stan-

dards. Each PURESPEED I/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and

VREF2 resources allowing each bank to be completely independent from each other. Figure 2-26 shows the seven

banks and their associated supplies. Table 2-7 lists the maximum number of I/Os per bank for the whole LatticeSC

family.

In the LatticeSC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI33 and PCIX33)

are powered using VCCIO. In addition to the bank VCCIO supplies, the LatticeSC devices have a VCC core logic power

supply, and a VCCAUX supply that power all differential and referenced buffers. VCCAUX also powers a predriver of

single-ended output buffers to enhance buffer performance.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-

enced input buffers. In the LatticeSC devices any I/O pin in a bank can be configured to be a dedicated reference

voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages.

Differential drivers have user selectable internal or external bias. External bias is brought in by the VREF1 pin in the

bank. External bias for differential buffers is needed for applications that requires tighter than standard output com-

mon mode range.

Since a bank can have only one external bias circuit for differential drivers, LVDS and RSDS differential outputs can

be mixed in a bank but not with HYPT (HyperTransport).

If a differential driver is configured in a bank, one pin in that bank becomes a DIFFR pin. This DIFFR pin must be

connected to ground via an external 1K +/-1% ohm resistor. Note that differential drivers are not supported in

banks 1, 4 and 5.

In addition, there are dedicated Terminating Supply (VTT) pins to be used as terminating voltage for one of the two

ways to perform parallel terminations. These VTT pins are available in banks 2-7, these pins are not available in

some packages. When VTT termination is not required, or used to provide the common mode termination voltage

(VCMT), these pins can be left unconnected on the device. If the internal or external VCMT function for differential

input termination is used, the VTT pins should be unconnected and allowed to float.

There are further restrictions on the use of VTT pins, for additional details refer to technical information at the end of

this data sheet.

2-24

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