LFSC3GA40E-7FF1020I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA40E-7FF1020I Datasheet PDF : 237 Pages
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Lattice Semiconductor
Figure 2-26. LatticeSC Banks
Architecture
LatticeSC/M Family Data Sheet
VCCIO7
VREF1[7]
VTT7
VREF2[7]
GND
VCCIO6
VREF1[6]
VTT6
VREF2[6]
GND
SERDES
Bank 1
SERDES
Bank 5
Bank 4
VCCIO2
VREF1[2]
VTT2
VREF2[2]
GND
VCCIO3
VREF1[3]
VTT[3]
VREF2[3]
GND
Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family
Device
LFSC/M15
LFSC/M25
LFSC/M40
Bank1
104
80
136
Bank2
28
36
60
Bank3
60
84
96
Bank4
72
100
124
Bank5
72
100
124
Bank6
60
84
96
Bank7
28
36
60
Note: Not all the I/Os of the Banks are available in all the packages
LFSC/M80
80
96
132
184
184
132
96
LFSC/M115
136
136
156
208
208
156
136
The LatticeSC devices contain three types of PURESPEED I/O buffers:
1. Left and Right Sides (Banks 2, 3, 6 and 7)
These buffers can support LVCMOS standards up to 2.5V. A differential output driver (for LVDS, RSDS, and
HYPT) is provided on all primary PIO pairs (A and B) and differential receivers are available on all pairs. Com-
plimentary drivers are available. Adaptive input logic is available on PIOs A or C.
2. Top Side (Bank 1)
These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential
receivers are provided on all PIO pairs but differential drivers for LVDS, RSDS, and HYPT are not available.
Adaptive input logic is not available on this side. Complimentary output drivers are available.
2-25
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