LFSC3GA115EP1-7F900C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA115EP1-7F900C Datasheet PDF : 237 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
MLVDS
The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled imped-
ance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs.
MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The
scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals.
Figure 3-1. MLVDS Multi-Point Output Example
2.5V
50
Heavily loaded backplane, effective Zo ~ 50 to 70 ohms differential
50-70 ohms, +/- 1%
50-70 ohms, +/- 1%
2.5V
50
2.5V
50
+
-
2.5V
50
2.5V
50
...
+-
2.5V
50
2.5V
50
+-
2.5V
50
+
-
Table 3-1. MLVDS DC Conditions1
Over Recommended Operating Conditions
Symbol
Description
ZOUT
Output impedance
RTLEFT
Left end termination
RTRIGHT
Right end termination
VOH
Output high voltage
VOL
Output low voltage
VOD
Output differential voltage
VCM
Output common mode voltage
IDC
DC output current
1. For input buffer, see LVDS table.
Nominal
Zo = 50 Zo = 70
50
50
50
70
50
70
1.50 1.575
1.00 0.925
0.50
0.65
1.25
1.25
20.0
18.5
Units
ohm
ohm
ohm
V
V
V
V
mA
3-8
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