LFSC3GA115EP1-7F900C View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA115EP1-7F900C

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

LatticeSC/M External Switching Characteristics3

Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

General I/O Pin Parameters (using Primary Clock without PLL)2

tCO

Global Clock Input to Output - PIO Output Reg-

ister

2.83

5.74

2.83

6.11

2.83

6.49

ns

tSU

Global Clock Input Setup - PIO Input Register

without fixed input delay

-0.66

—

-0.66

—

-0.66

—

ns

tH

Global Clock Input Hold - PIO Input Register

without fixed input delay

1.73 — 1.95 — 2.16 —

ns

tSU_IDLY

Global Clock Input Setup - PIO Input Register

with input delay

0.86

—

1.03

—

1.20

—

ns

tH_IDLY

Global Clock Input Hold - PIO Input Register

with input delay

-0.17 — -0.17 — -0.17 —

ns

fMAX_PFU Global Clock frequency of PFU register

—

700

—

700

—

700 MHz

fMAX_IO

Global Clock frequency of I/O register

— 1000 — 1000 — 1000 MHz

tGC_SKEW Global Clock skew

—

89

—

103

—

116

ps

General I/O Pin Parameters (using Primary Clock with PLL)1, 2

tCO

Global Clock Input to Output - PIO Output Reg-

ister

2.25

4.81

2.25

5.08

2.25

5.37

ns

tSU

Global Clock Input Setup - PIO Input Register

without fixed input delay

-0.07

—

-0.07

—

-0.07

—

ns

tH

Global Clock Input Hold - PIO Input Register

without fixed input delay

0.80 — 0.93 — 1.04 —

ns

General I/O Pin Parameters (using Edge Clock without PLL)2

tCO

Edge Clock Input to Output - PIO Output Regis-

ter

2.38

4.77

2.38

5.04

2.38

5.33

ns

tSU

Edge Clock Input Setup - PIO Input Register

without fixed input delay

-0.08 — -0.08 — -0.08 —

ns

tH

Edge Clock Input Hold - PIO Input Register

0.49 — 0.58 — 0.66 —

ns

tSU_IDLY

Edge Clock Input Setup - PIO Input Register

with input delay

0.81 — 0.97 — 1.12 —

ns

tH_IDLY

Edge Clock Input Hold - PIO Input Register with

input delay

-0.34

—

-0.34

—

-0.34

—

ns

tEC_SKEW Edge Clock skew

—

28

—

32

—

36

ps

General I/O Pin Parameters (using Latch FF without PLL)2

tSU

Latch FF, Input Setup - PIO Input Register with-

out fixed input delay

-0.14

—

-0.14

—

-0.14

—

ns

tH

Latch FF, Input Hold - PIO Input Register without

fixed input delay

0.58

—

0.68

—

0.77

—

ns

tSU_IDLY

Latch FF, Input Setup - PIO Input Register with

input delay

0.70

—

0.68

—

0.77

—

ns

tH_IDLY

Latch FF, Input Hold - PIO Input Register with

input delay

-0.30

—

-0.30

—

-0.30

—

ns

1. No PLL delay tuning (clock injection removal mode, system clock feedback).

2. Using LVCMOS25 12mA I/O. Timing adders for other supported I/O technologies are specified in the LatticeSC Family Timing Adders table.

3. Complete Timing Parameters for a user design are incorporated when running ispLEVER. This is a sampling of the key timing parameters.

Timing specs are for non-AIL applications.

3-13

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