LFSC3GA115EP1-7F900C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA115EP1-7F900C Datasheet PDF : 237 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
Typical Building Block Function Performance
Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%
Pin to Pin Performance (LVCMOS25 12 mA Drive)
Function
Basic Functions
32-bit Decoder
Combinatorial (Pin to LUT to Pin)
Embedded Memory Functions (Single Port RAM)
Pin to EBR Input Register Setup (Global Clock)
EBR Output Clock to Pin (Global Clock)
Distributed (PFU) RAM (Single Port RAM)
Pin to PFU RAM Register Setup (Global Clock)
PFU RAM Clock to Pin (Global Clock)
*Typical performance per function
-7*
Units
6.65
ns
5.58
ns
1.66
ns
8.54
ns
1.32
ns
6.83
ns
Register-to-Register Performance
Function
Basic Functions
32-Bit Decoder
64-Bit Decoder
16:1 MUX
32:1 MUX
16-Bit Adder
64-Bit Adder
16-Bit Counter
64-Bit Counter
32x8 SP RAM (PFU, Output Registered)
128x8 SP RAM (PFU, Output Registered)
Embedded Memory Functions
Single Port RAM (512x36 Bits)
True Dual Port RAM 1024x18 Bits (No EBR Out Reg)
True dual port RAM 1024x18 Bits (EBR Reg)
FIFO port (A: x36 bits, B: x9 Bits, No EBR Out Reg)
FIFO port (A: x36 bits, B: x9 Bits, EBR Reg)
True DP RAM Width Cascading (1024x72)
DSP Functions
9x9 1-stage Multiplier
18x18 1-Stage Multiplier
9x9 3-Stage Pipelined Multiplier
18x18 4-Stage Pipelined Multiplier
9x9 Constant Multiplier
*Typical performance per function
-7*
539
517
1003
798
672
353
719
369
768
545
372
326
372
353
375
372
209
155
373
314
372
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3-11
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