LFSC3GA25E-5FN900I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA25E-5FN900I Datasheet PDF : 237 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
LatticeSC/M sysCONFIG Port Timing (Continued)
Over Recommended Operating Conditions
Parameter
Description
sysCONFIG Asynchronous Peripheral Configuration Mode
tWRAP
tSAP
tRDYAP
WRN, CS0N and CS1 Pulse Width
D[7:0] Setup Time
RDY Delay
Min.
5
1.5
—
tBAP
RDY Low
1
tWR2AP
Earliest WRN After RDY Goes High
tDENAP
RDN to D[7:0] Enable/Disable
tDAP
CCLK to DOUT
sysCONFIG Slave Serial Configuration Mode
tSSS
DIN Setup Time
tHSS
DIN Hold Time
tCHSS
CCLK High Time
tCLSS
CCLK Low Time
fCSS
CCLK Frequency
tDSS
CCLK to DOUT
sysCONFIG Slave Parallel Configuration Mode
tS1SP
tH1SP
tS2SP
tH2SP
tCHSP
tCL
fCSP
CS0N, CS1, WRN Setup Time
CS0N, CS1, WRN Hold Time
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
0
—
—
5.2
0
3.75
3.75
—
—
5.2
0
5.2
0
3.75
3.75
—
sysCONFIG MPI Port
Parameter
tMPICTRL_SET
tMPIADR_SET
tMPIDAT_SET
tMPIDPAR_SET
tMPI_HLD
tMPICTRL_DEL
tMPIDAT_DEL
tMPIDPAR_DEL
fMPI_CLK_FRQ
Description
MPI Control (MPCSTRBN, MPCWRN,
MPCCLK, etc.) to MPCCLK Setup Time
MPI Address to MPCCLK Setup Time
MPI Write Data to MPCCLK Setup Time
MPI Write Parity Data to MPCCLK Setup
Time
All Hold Times
MPCCLK to MPI Control (MPCTA, MPC-
TEA, MPCRETRY)
MPCCLK to MPI Data
MPCCLK to MPI Parity Data
MPCCLK Frequency
-7
Min. Max.
4.9
—
3.9
—
4.9
—
3.9
—
0
—
—
5.6
—
5.6
—
4.9
—
100
-6
Min. Max.
5.2
—
4.2
—
5.2
—
4.2
—
0
—
—
6.7
—
6.7
—
5.7
—
83
Max.
-
-
8
8
—
7.5
7.5
—
—
—
—
150
7.5
—
—
—
—
—
—
150
Units
ns
ns
ns
CCLK
periods
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
-5
Min. Max.
5.5
—
4.5
—
5.5
—
4.5
—
0
—
—
8.7
—
8.7
—
7.7
—
66
Units
ns
ns
ns
ns
ns
ns
ns
ns
MHz
3-28
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