LFSC3GA25E-5FN900I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA25E-5FN900I Datasheet PDF : 237 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol
fMAX
tBTCP
tBTCPH
tBTCPL
tBTS
tBTH
tBTRF
tBTCO
tBTCODIS
tBTCOEN
tBTCRS
tBTCRH
tBUTCO
tBTUODIS
tBTUPOEN
Parameter
TCK [BSCAN] Clock Pulse Width
TCK [BSCAN] Clock Pulse Width High
TCK [BSCAN] Clock Pulse Width Low
TCK [BSCAN] Setup Time
TCK [BSCAN] Hold Time
TCK [BSCAN] Rise/Fall Time
TAP Controller Falling Edge of Clock to Valid Output
TAP Controller Falling Edge of Clock to Valid Disable
TAP Controller Falling Edge of Clock to Valid Enable
BSCAN Test Capture Register Setup Time
BSCAN Test Capture Register Hold Time
BSCAN Test Update Register, Falling Edge of Clock
to Valid Output
BSCAN Test Update Register, Falling Edge of Clock
to Valid Disable
BSCAN Test Update Register, Falling Edge of Clock
to Valid Enable
Min.
—
40
50
—
—
8
10
20
20
—
8
10
—
—
—
Figure 3-14. JTAG Port Timing Waveforms
TMS
Max.
25
—
—
10
10
—
—
—
—
10
—
—
25
25
25
Units
MHz
ns
mV/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDI
TCK
TDO
Data to be
captured
from I/O
Data to be
driven out
to I/O
tBTCPH
tBTS
tBTCPL
tBTH
tBTCP
tBTCOEN
Valid Data
tBTCO
tBTCRS
tBTCRH
Data Captured
tBTUPOEN
tBUTCO
Valid Data
tBTCODIS
Valid Data
tBTUODIS
Valid Data
3-29
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