LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Switching Test Conditions

Figure 3-15 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are shown in Table 3-4.

Figure 3-15. Output Test Load, LVTTL and LVCMOS Standards

DUT

Test Poi nt

CL

Table 3-4. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

CL

Timing Ref.

VT

LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = VCCIO/2

—

LVTTL and other LVCMOS settings (L -> H, H -> L)

30pF LVCMOS 1.8 = VCCIO/2

—

LVCMOS 1.5 = VCCIO/2

—

LVCMOS 1.2 = VCCIO/2

—

LVCMOS 2.5 I/O (Z -> H)

VCCIO/2

VOL

LVCMOS 2.5 I/O (Z -> L)

LVCMOS 2.5 I/O (H -> Z)

30pF VCCIO/2

VOH - 0.15

VOH

VOL

LVCMOS 2.5 I/O (L -> Z)

VOL + 0.15

VOH

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-30

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