LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA80E-7FN256I Datasheet PDF : 237 Pages
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Lattice Semiconductor
Pinout Information
LatticeSC/M Family Data Sheet
Signal Descriptions (Cont.)
Signal Name
I/O
MPI_STRBN
I
MPI_ADDR[31:14]
I
MPI_DAT[n:0]
I/O
MPI_PAR[m:0]
I/O
MPI_TA
O
MPI_TEA
O
MPI_RETRY
O
Multi-chip Alignment (User I/O if not used.)
MCA_DONE_OUT
O
MCA_DONE_IN
I
MCA_CLK_P[1:2]_OUT
O
MCA_CLK_P[1:2]_IN
I
TEMP
—
Miscellaneous Dedicated Pins
XRES
—
DIFFRx
—
SERDES Block (Dedicated Pins)
[A:D]_HDINPx_[L/R]
I
[A:D]_HDINNx_[L/R]
I
[A:D]_HDOUTPx_[L/R]
O
[A:D]_HDOUTNx_[L/R]
O
[A:D]_REFCLKP_[L/R]
I
[A:D]_REFCLKN_[L/R]
I
Description
Driven active low indicates the start of a transaction on the PowerPC
bus. MPI will strobe the address bus at next rising edge of clock.
Address bus driven by a PowerPC bus master. Only 18-bit width is
needed. It has to be the least significant bit of the PowerPC 32-bit
address A[31:14].
Selectable data bus width from 8, and 16-bit. Driven by a bus master
in a write transaction. Driven by MPI in a read transaction.
Selectable parity bus width from 1, 2, and 3-bit. MPI_DP[0] for
MPI_D[7:0], MPI_DP[1] for MPI_D[15:8] and MPI_DP[2] for
MPI_D[23:16].
Transfer acknowledge. Driven active low indicates that MPI received
the data on the write cycle or returned data on the read cycle.
Transfer Error Acknowledge. Driven active low indicates that MPI
detects a bus error on the internal system bus for current transaction.
Active low MPI Retry requests the MPC860 to relinquish the bus and
retry the cycle.
Multi-chip alignment done output (to second MCA chip)
Multi-chip alignment done input (from second MCA chip)
Multi-chip alignment clock [1:2] output (sourced by MCA master chip)
Multi-chip alignment clock [1:2] input (from MCA master chip
Temperature sensing diode pin. Dedicated pin. Accuracy is typically
+/- 10°C.
External reference resistor between this pin and ground. The refer-
ence resistor is used to calibrate the programmable terminating resis-
tors used in the I/Os. Dedicated pin. Value: 1K ± 1% ohm.
Only used if a differential driver is used in a bank. This DIFFRx must
be connected to ground via an external 1K ±1% ohm resistor for all
banks that have a differential driver.
High-speed input (positive) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
High-speed input (negative) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
High-speed output (positive) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
High-speed output (negative) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
Ref clock input (positive), aux channel on left [L] or right [R] side of
device.
Ref clock input (negative), aux channel on left [L] or right [R] side of
device.
4-5
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