LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

January 2008

Signal Descriptions

Signal Name

General Purpose

P[Edge] [Row/Column Number*]_[A/B/C/D]

VREF1_x, VREF2_x

NC

Non-SERDES Power Supplies

VCCIOx

VCC121

VTT_x

GND

VCC

VCCAUX

VCCJ

PROBE_VCC

LatticeSC/M Family Data Sheet

Pinout Information

Data Sheet DS1004

I/O

Description

[Edge] indicates the edge of the device on which the pad is located.

Valid edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PIC row or the column of the

device on which the PIC exists. When Edge is T (Top) or (Bottom),

only need to specify Row Number. When Edge is L (Left) or R (Right),

only need to specify Column Number.

[A/B/C/D] indicates the PIO within the PIC to which the pad is con-

I/O nected.

Some of these user programmable pins are shared with special func-

tion pins. These pin when not used as special purpose pins can be

programmed as I/Os for user logic.

During configuration the user-programmable I/Os are tri-stated with an

internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor

enabled after configuration.

The reference supply pins for I/O bank x. Any I/O pin in a bank can be

— assigned as a reference supply pin, but software defaults use desig-

nated pin.

—

No connect. NC pins should not be connected to any active signals,

VCC or GND.

— VCCIO - The power supply pins for I/O bank x. Dedicated pins.

1.2V supply for configuration logic, PLLs and SERDES Rx, Tx and

—

PLL. All VCC12 pins must be connected. As VCC12 supplies power

for analog circuitry, VCC12 should be quiet and isolated from noisy

digital board supplies.

Termination voltage for bank x. When VTT termination is not required,

or used to provide the common mode termination voltage (VCMT),

—

these pins can be left unconnected on the device. VCMT function is

not used in the bank. If the internal or external VCMT function for dif-

ferential input termination is used, the VTT pins should be uncon-

nected and allowed to float.

—

GND - Ground. Dedicated pins. All grounds must be electrically con-

nected at the board level.

—

VCC - The power supply pins for core logic. Dedicated pins (1.2V/

1.0V).

—

VCCAUX - Auxiliary power supply pin - powers all differential and

referenced input buffers. Dedicated pins (2.5V).

— VCCJ - The power supply pin for JTAG Test Access Port.

VCC signal - Connected to internal VCC node. Can be used for feed-

— back to control an external board power converter. Can be uncon-

nected if not used.

© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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DS1004 Pinouts_01.8

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