ADE7858AACPZ-RL View Datasheet(PDF) - Analog Devices
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ADE7858AACPZ-RL Datasheet PDF : 96 Pages
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Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Table 49. CONSEL[1:0] Bits in Energy Registers
Energy Registers
CONSEL[1:0] = 00
AWATTHR, AFWATTHR
VA × IA
BWATTHR, BFWATTHR
VB × IB
CWATTHR, CFWATTHR
AVARHR, AFVARHR
BVARHR, BFVARHR
VC × IC
VA × IA’
VB × IB’
CVARHR, CFVARHR
AVAHR
BVAHR
VC × IC’
VA rms × IA rms
VB rms × IB rms
CVAHR
VC rms × IC rms
CONSEL[1:0] = 01
VA × IA
VB = VA − VC1
VB × IB
VC × IC
VA × IA’
VB = VA − VC1
VB1 × IB
VC × IC’
VA rms × IA rms
VB rms × IB rms
VB = VA − VC1
VC rms × IC rms
CONSEL[1:0] = 10
VA × IA
VB = −VA − VC
VB × IB
VC × IC
VA × IA’
VB = −VA − VC
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VB = −VA − VC
VC rms × IC rms
CONSEL[1:0] = 11
VA × IA
VB = −VA
VB × IB
VC × IC
VA × IA’
VB = −VA
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VB = −VA
VC rms × IC rms
1 In a 3-phase, 3-wire case (CONSEL[1:0] = 01), the device computes the rms value of the line voltage between Phase A and Phase C and stores the result into the BVRMS
register (see the Voltage RMS in 3-Phase, 3-Wire Delta Configurations section). Consequently, the device computes powers associated with Phase B that do not have
physical meaning. To avoid any errors in the frequency output pins (CF1, CF2, or CF3) related to the powers associated with Phase B, disable the contribution of
Phase B to the energy to frequency converters by setting Bit TERMSEL1[1], Bit TERMSEL2[1], or Bit TERMSEL3[1] to 0 in the COMPMODE register (see the Energy to
Frequency Conversion section).
Table 50. LCYCMODE Register (Address 0xE702)
Default
Bits
Bit Name
Value
Description
0
LWATT
0
0: places the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) into regular accumulation mode.
1: places the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) into line cycle accumulation mode.
1
LVAR
0
0: places the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) into regular
accumulation mode. This bit is always set to 0 for the ADE7854A.
1: places the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) into line cycle
accumulation mode.
2
LVA
0
0: places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) into regular
accumulation mode.
1: places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) into line cycle
accumulation mode.
3
ZXSEL[0]
1
0: Phase A is not selected for zero-crossing counts in the line cycle accumulation mode.
1: Phase A is selected for zero-crossing counts in the line cycle accumulation mode. The
accumulation time is shortened accordingly when more than one phase is selected for
zero-crossing detection.
4
ZXSEL[1]
1
0: Phase B is not selected for zero-crossing counts in the line cycle accumulation mode.
1: Phase B is selected for zero-crossing counts in the line cycle accumulation mode.
5
ZXSEL[2]
1
0: Phase C is not selected for zero-crossing counts in the line cycle accumulation mode.
1: Phase C is selected for zero-crossing counts in the line cycle accumulation mode.
6
RSTREAD
1
0: disables read with reset of all energy registers. Clear this bit to 0 when Bits[2:0] (LWATT,
LVAR, and LVA) are set to 1.
1: enables read with reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. This means that a read of those registers resets them to 0.
7
Reserved
0
Reserved. This bit does not manage any functionality.
Rev. C | Page 93 of 96
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