ADE7858AACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7858AACPZ-RL Datasheet PDF : 96 Pages
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ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
Table 51. HSDC_CFG Register (Address 0xE706)
Default
Bits
Bit Name
Value
Description
0
HCLK
0
0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
1
HSIZE
0
0: HSDC transmits the 32-bit registers in 32-bit packages, MSB first.
1: HSDC transmits the 32-bit registers in 8-bit packages, MSB first.
2
HGAP
0
0: no gap is introduced between packages.
1: introduces a gap of seven HCLK cycles between packages.
[4:3]
HXFER[1:0]
00
00 = for the ADE7854A, HSDC transmits sixteen 32-bit words in the following order: IAWV,
VAWV, IBWV, VBWV, ICWV, and VCWV; one 32-bit word equal to 0, AVA, BVA, CVA, AWATT,
BWATT, and CWATT; and three 32-bit words equal to 0. For the ADE7858A, HSDC transmits
sixteen 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, and VCWV and
one 32-bit word equal to 0, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.
For the ADE7868A and ADE7878A, HSDC transmits sixteen 32-bit words in the following
order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT,
AVAR, BVAR, and CVAR.
01 = for the ADE7854A and ADE7858A, HSDC transmits six instantaneous values of currents
and voltages in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, and VCWV, and one
32-bit word equal to 0. For the ADE7868A and ADE7878A, HSDC transmits seven
instantaneous values of currents and voltages in the following order: IAWV, VAWV, IBWV,
VBWV, ICWV, VCWV, and INWV.
10 = for the ADE7854A, HSDC transmits six instantaneous values of phase powers in the
following order: AVA, BVA, CVA, AWATT, BWATT, and CWATT and three 32-bit words equal to
0. For the ADE7858A, ADE7868A, and ADE7878A, HSDC transmits nine instantaneous values
of phase powers in the following order: AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR,
and CVAR.
11 = reserved. If set, the ADE7854A, ADE7858A, ADE7868A, and ADE7878A behave as if
HXFER[1:0] = 00.
5
HSAPOL
0
0: SS/HSA output pin is active low.
1: SS/HSA output pin is active high.
[7:6]
Reserved
00
Reserved. These bits do not manage any functionality.
Table 52. LPOILVL Register (Address 0xEC00)1
Bits
Bit Name
Default Value Description
[2:0]
LPOIL[2:0]
000
PSM2 threshold selection; see Table 10.
[7:3]
LPLINE[4:0]
00000
For PSM2 interrupt mode, the measurement period is 0.02 × (LPLINE + 10) seconds.
For PSM2 IRQ1 only mode, the measurement period is 0.02 × (LPLINE + 1; use an external
timer to wait for this period.
1 The LPOILVL register is available for the ADE7868A and ADE7878A only; it is reserved for the ADE7854A and ADE7858A.
Table 53. CONFIG2 Register (Address 0xEC01)
Bits
Bit Name
Default Value Description
0
EXTREFEN
0
Setting this bit to 0 signifies that the internal voltage reference is used in the ADCs.
Setting this bit is set to 1 connects an external reference to Pin 17, REFIN/OUT.
1
I2C_LOCK
0
Setting this bit is set to 0 allows the SS/HSA pin to be toggled three times to activate the SPI
port. When I2C is the active serial port, this bit must be set to 1 to lock it in. From this moment
on, spurious toggling of the SS/HSA pin and an eventual switch to using the SPI port is no
longer possible. When SPI is the active serial port, any write to the CONFIG2 register locks the
port. From this moment on, switching to the I2C port is no longer possible. Once locked, the
serial port choice is maintained when the PSMx power modes of the ADE7854A, ADE7858A,
ADE7868A, and ADE7878A change.
2
IRQ0_DIS
0
When set to 1, the IRQ0 pin is disabled in PSM2 mode.
[7:3]
Reserved
0
Reserved. These bits do not manage any functionality.
Rev. C | Page 94 of 96
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