AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation
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AT91SAM9G46B-CU Datasheet PDF : 1277 Pages
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48.14 DDRSDRC Timings
The DDRSDRC controller satisfies the timings of standard DDR2, LPDDR, SDR and LP-SDR modules.
DDR2, LPDDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
DDR2-400 limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK/CK#)
LPDDR (1.8V, 30 pF on data/control, 10 pF on CK)
̶ ta = 5.0 ns, fmax = 125 MHz
̶ ta = 6.0 ns, fmax = 110 MHz
̶ ta = 7.5 ns, fmax = 95 MHz
SDR-100 (3.3V, 50 pF on data/control, 10 pF on CK)
SDR-133 (3.3V, 50 pF on data/control, 10 pF on CK)
LP-SDR-133 (1.8V, 30 pF on data/control, 10 pF on CK)
48.15 Peripheral Timings
48.15.1 SPI
48.15.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write
modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or
SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 48.9 “I/Os”),
the max SPI frequency is the one from the pad.
Master Read Mode
fSPCKMax
=
----------------------------1------------------------------
SPI0(or SPI3) + tvalid
tvalid is the slave time response to output data after deleting an SPCK edge. For a non-volatile memory with tvalid (or
tv) = 12 ns Max, fSPCKMax = 38.5 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold
timings SPI7/SPI8(or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave
read mode is given by SPCK pad.
Slave Write Mode
fSPCKMax = -S----P----I--6---(---o---r----S----P-1----I--9---)---+-----t--s---e---t-u---p--
For 3.3V I/O domain and SPI6, fSPCKMax = 33 MHz. tsetup is the setup time from the master before sampling
data.
SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
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