STM8S003K3 STM8S003F3
(3) Measured from interrupt event to interrupt vector fetch.
(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
Electrical characteristics
9.3.2.6 Total current consumption and timing in forced reset state
Symbol
Table 29: Total current consumption and timing in forced reset state
Parameter
Conditions
Typ
Max(1) Unit
IDD(R)
tRESETBL
Supply current in reset
state(2)
Reset pin release to
vector fetch
VDD = 5 V
VDD = 3.3 V
400
μA
300
150
μs
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS.
9.3.2.7
Symbol
IDD(TIM1)
Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V
Table 30: Peripheral current consumption
Parameter
Typ.
TIM1 supply current(1)
210
IDD(TIM2)
TIM2 supply current(1)
130
IDD(TIM4)
TIM4 timer supply current(1)
50
IDD(UART1)
UART1 supply current(2)
120
IDD(SPI)
SPI supply current(2)
45
IDD(I2C)
I2C supply current(2)
65
IDD(ADC1)
ADC1 supply current when converting(3)
1000
Unit
μA
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