STM8S105K6U3C View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM8S105K6U3C

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C

STMicroelectronics 

Option bytes

STM8S105xx

8

Addr.

Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP

option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication

protocol and debug module user manual (UM0470) for information on SWIM programming

procedures.

Table 12: Option bytes

Option

name

Option Option bits

byte no.

7

6

5

4

3

2

1

Factory

default

0

setting

0x4800 Read-out OPT0 ROP [7:0]

00h

protection

(ROP)

0x4801 User boot OPT1 UBC [7:0]

00h

code(UBC)

0x4802

NOPT1 NUBC [7:0]

FFh

0x4803

0x4804

Alternate

function

remapping

(AFR)

OPT2

NOPT2

AFR7

NAFR7

AFR6 AFR5 AFR4

NAFR6 NAFR5 NAFR4

AFR3

NAFR3

AFR2 AFR1 AFR0 00h

NAFR2 NAFR1 NAFR0 FFh

0x4805h Miscell.

option

OPT3 Reserved

HSI

TRIM

LSI_ EN IWDG WWDG WWDG 00h

_HW _HW _HALT

0x4806

NOPT3 Reserved

NHSI

TRIM

NLSI_

EN

NIWDG NWWDG NWW FFh

_HW _HW G_HALT

0x4807 Clock

option

OPT4 Reserved

EXT CLK CKAWU PRS C1 PRS C0 00h

SEL

0x4808

NOPT4 Reserved

NEXT NCKA NPRSC1 NPR FFh

CLK

WUSEL

SC0

0x4809 HSE clock OPT5 HSECNT [7:0]

00h

startup

0x480A

NOPT5 NHSECNT [7:0]

FFh

0x480B Reserved OPT6 Reserved

00h

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DocID14771 Rev 9

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