PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
12.0 TIMER1
Note:
This data sheet summarizes the features
of the PIC32MX1XX/2XX/5XX 64/100-pin
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
This family of PIC32 devices features one synchronous/
asynchronous 16-bit timer that can operate as a free-
running interval timer for various timing applications and
counting external events. This timer can also be used
with the Low-Power Secondary Oscillator (SOSC) for
Real-Time Clock (RTC) applications. The following
modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
12.1 Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC)
Data Bus<31:0>
<15:0>
Reset
TMR1
16-bit Comparator
Equal
PR1
TSYNC
1
Sync
0
0
T1IF
Event Flag
1
TGATE
QD
Q
TGATE
TCS
ON
SOSCO/T1CK
SOSCI
x1
SOSCEN
Gate
Sync
10
PBCLK
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
Note:
The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the FSOSCEN
bit in Configuration Word, DEVCFG1.
2014-2017 Microchip Technology Inc.
DS60001290E-page 159