12.2 Control Registers
TABLE 12-1: TIMER1 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0600
T1CON
31:16
15:0
—
ON
—
—
—
—
—
—
SIDL TWDIS TWIP
—
—
—
—
—
—
—
TGATE
—
—
—
TCKPS<1:0>
—
—
—
—
TSYNC TCS
—
0000
—
0000
0610
TMR1
31:16
15:0
—
—
—
—
—
—
—
—
—
TMR1<15:0>
—
—
—
—
—
—
—
0000
0000
0620
PR1
31:16
15:0
—
—
—
—
—
—
—
—
—
PR1<15:0>
—
—
—
—
—
—
—
0000
FFFF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for
more information.