PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 18-1: I2CXCON: I2C ‘x’ CONTROL REGISTER (‘x’ = 1 AND 2)

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

31:24

U-0

—

U-0

U-0

U-0

U-0

U-0

—

—

—

—

—

U-0

23:16

—

U-0

U-0

U-0

U-0

U-0

—

—

—

—

—

15:8

R/W-0

ON(1)

U-0

—

R/W-0

SIDL

R/W-1, HC

SCLREL

R/W-0

STRICT

R/W-0

A10M

7:0

R/W-0

GCEN

R/W-0

STREN

R/W-0

ACKDT

R/W-0, HC

ACKEN

R/W-0, HC

RCEN

R/W-0, HC

PEN

Bit

25/17/9/1

U-0

—

U-0

—

R/W-0

DISSLW

R/W-0, HC

RSEN

Bit

24/16/8/0

U-0

—

U-0

—

R/W-0

SMEN

R/W-0, HC

SEN

Legend:

R = Readable bit

-n = Value at POR

HC = Cleared in Hardware

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: I2C Enable bit(1)

1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins

0 = Disables the I2C module; all I2C pins are controlled by PORT functions

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

bit 12

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

SCLREL: SCLx Release Control bit (when operating as I2C slave)

1 = Release SCLx clock

0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at

beginning of slave transmission. Hardware clear at end of slave reception.

bit 11

bit 10

bit 9

bit 8

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

STRICT: Strict I2C Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate

addresses in reserved address space.

0 = Strict I2C Reserved Address Rule not enabled

A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled

0 = Slew rate control enabled

SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification

0 = Disable SMBus input thresholds

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

DS60001290E-page 194

 2014-2017 Microchip Technology Inc.

Share Link: