PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 18-1: I2CXCON: I2C ‘x’ CONTROL REGISTER (CONTINUED)(‘x’ = 1 AND 2)

bit 7

GCEN: General Call Enable bit (when operating as I2C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0 = General call address disabled

bit 6

STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)

Used in conjunction with SCLREL bit.

1 = Enable software or receive clock stretching

0 = Disable software or receive clock stretching

bit 5

ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

1 = Send NACK during Acknowledge

0 = Send ACK during Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit 

(when operating as I2C master, applicable during master receive)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. 

Hardware clear at end of master Acknowledge sequence.

0 = Acknowledge sequence not in progress

bit 3

RCEN: Receive Enable bit (when operating as I2C master)

1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.

0 = Receive sequence not in progress

bit 2

PEN: Stop Condition Enable bit (when operating as I2C master)

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0 = Stop condition not in progress

bit 1

RSEN: Repeated Start Condition Enable bit (when operating as I2C master)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of 

master Repeated Start sequence.

0 = Repeated Start condition not in progress

bit 0

SEN: Start Condition Enable bit (when operating as I2C master)

1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0 = Start condition not in progress

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 195

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