PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

31:24

23:16

15:8

7:0

U-0

U-0

—

—

R/W-0, HC

U-0

RDSTART

—

R/W-0

U-0

ON(1)

—

R/W-0

R/W-0

CSF<1:0>(2)

U-0

—

U-0

—

R/W-0

SIDL

R/W-0

ALP(2)

U-0

U-0

—

—

U-0

U-0

—

—

R/W-0

R/W-0

ADRMUX<1:0>

R/W-0

CS2P(2)

R/W-0

CS1P(2)

U-0

—

U-0

—

R/W-0

PMPTTL

U-0

—

Bit

25/17/9/1

U-0

—

R/W-0

DUALBUF

R/W-0

PTWREN

R/W-0

WRSP

Bit

24/16/8/0

U-0

—

U-0

—

R/W-0

PTRDEN

R/W-0

RDSP

Legend:

R = Readable bit

-n = Value at POR

HC = Hardware cleared

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 RDSTART: Start a Read on the PMP Bus bit(3)

1 = Start a read cycle on the PMP bus

0 = No effect

This bit is cleared by hardware at the end of the read cycle when the BUSY bit (PMMODE<15>) = 0.

bit 22-18 Unimplemented: Read as ‘0’

bit 17 DUALBUF: Parallel Master Port Dual Read/Write Buffer Enable bit

This bit is only valid in Master mode.

1 = PMP uses separate registers for reads and writes

Reads: PMRADDR and PMRDIN

Writes: PMRWADDR and PMDOUT

0 = PMP uses legacy registers for reads and writes

Reads/Writes: PMADDR and PMRDIN

bit 16 Unimplemented: Read as ‘0’

bit 15 ON: Parallel Master Port Enable bit(1)

1 = PMP enabled

0 = PMP disabled, no off-chip access performed

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = Lower 8 bits of address are multiplexed on PMD<15:0> pins

10 = All 16 bits of address are multiplexed on PMD<7:0> pins

01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8>

00 = Address and data appear on separate pins

bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit

1 = PMP module uses TTL input buffers

0 = PMP module uses Schmitt Trigger input buffer

bit 9

PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port enabled

0 = PMWR/PMENB port disabled

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when their corresponding pins are used as address lines.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 209

Share Link: