21.1 Control Registers
TABLE 21-1: RTCC REGISTER MAP
Bits
31/15 30/14 29/13
28/12
27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0200
RTCCON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
CAL<9:0>
0000
—
—
—
— RTSECSEL RTCCLKON —
— RTCWREN RTCSYNC HALFSEC RTCOE 0000
0210
RTCALRM
31:16
15:0
—
ALRMEN
—
CHIME
—
—
—
PIV ALRMSYNC
—
—
AMASK<3:0>
—
—
—
—
—
—
—
—
— 0000
ARPT<7:0>
0000
0220
RTCTIME
31:16
15:0
HR10<3:0>
SEC10<3:0>
HR01<3:0>
SEC01<3:0>
MIN10<3:0>
MIN01<3:0>
xxxx
—
—
—
—
—
—
—
— xx00
0230
RTCDATE
31:16
15:0
YEAR10<3:0>
DAY10<3:0>
YEAR01<3:0>
DAY01<3:0>
MONTH10<3:0>
—
—
—
—
MONTH01<3:0>
WDAY01<3:0>
xxxx
xx00
0240
ALRMTIME
31:16
15:0
HR10<3:0>
SEC10<3:0>
HR01<3:0>
SEC01<3:0>
MIN10<3:0>
MIN01<3:0>
xxxx
—
—
—
—
—
—
—
— xx00
0250
ALRMDATE
31:16
15:0
—
—
—
DAY10<3:0>
—
—
—
—
—
DAY01<3:0>
MONTH10<3:0>
—
—
—
—
MONTH01<3:0>
WDAY01<3:0>
00xx
xx0x
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for
more information.